Product InfoSpecification
Ordering
|  | User configurable, on-board Altera Stratix III FPGA |
|  | Module software is fully compatible with Altera object files |
|  | No proprietary FPGA design tools required |
|  | Compatible with Altera’s free, web-based Quartus II design tools. |
|  | 160 digital I/O signals available for user specific applications |
|  | x4 PXI Express interface & integral DMA controller supports data streaming rates of more than 800 MB/s |
|  | 700 MHz digital I/O clock rate |
|  | 8MB of on-board SSRAM |
|  | Supports user defined expansion boards for custom interfaces |
|  | 3U PXI Express Card, available also in 3U PXI (GX3700) |
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DescriptionThe GX3700e is a user configurable, FPGA – based, 3U PXI Express card offering 160 digital I/O signals which can be configured for single-ended or differential interfaces. The card employs the Altera Stratix III FPGA, which can support SerDes data rates up to 1.2 Gb/s, digital I/O clock rates of 700 MHz, and features over 45,000 logic elements and 1.836 Kb of memory. The GX3700e is supplied with an integral expansion board providing access to the FPGA’s 160 I/Os. Alternatively, users can design their own custom expansion cards for specific applications - eliminating the need for additional external boards which are cumbersome and physically difficult to integrate into a test system. The design of the FPGA is done by using Altera’s free Quartus II Web Edition tool set. Once the user has compiled the FPGA design, the configuration file can be loaded directly into the FPGA or via an on-board EEPROM.
FeaturesThe GX3700e’s digital I/O signals are 5 volt tolerant. Logic families supported by the I/O interface include LVTTL, LVDS and LVCMOS. The FPGA device supports up to four phase lock loops for clock synthesis, clock generation and for support of the I/ O interface. An on-board 80 MHz oscillator is available for use with the FGPA device or alternatively, the PXI 10 MHz or 100 MHz clock can be used as a clock reference by the FPGA.
The FPGA has access to all of the PXI Express bus resources including the PXI 10 MHz clock, PXIe 100 MHz clock, PXIe Sync100, PXIe DStar triggers, the local bus, and the PXI triggers; allowing the user to create a custom instrument which incorporates all of the PXI Express bus resources. The GX3700e includes a DMA controller - facillitating high speed data streaming to and from the host controller. Control and access to the FPGA is provided via the GX3700e’s driver which includes DMA and interrupt support, tools for downloading the compiled FPGA code, and register read and write functionality.
Programmimg and SoftwareThe board is supplied with the GXFPGA library, a software package that includes a virtual instrument panel, and a Windows 32/64-bit DLL driver library and documentation. The virtual panel can be used to interactively program and control the instrument from a window that displays the instrument’s current settings and status. In addition, interface files are provided to support access to programming tools and languages such as ATEasy, LabView, LabView/Real-Time, C/C++, Microsoft Visual Basic®, Delphi, and Pascal. An On-Line help file and PDF User's Guide provides documentation that includes instructions for installing, using and programming the board. A separate software package - GtLinux - provides support for Linux 32/64 operating systems.
Applications |  | Automatic Test Equipment (ATE) |
|  | Semiconductor test |
|  | Custom interface emulation |
|  | Custom instrumentation |
|  | SerDes interfaces |
See Also
|  | GX3500 - Digital I/O FLEX FPGA PXI Card | |  | GX3640 - 3U PXI FGPA card with 40 ECL differental I/O channels | |  | GX3700 - 3U PXI High-Performance FPGA Board |
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| External Digital I/O Channels | | Logic Families | LVTTL, LVDS, configurable for 1.2 / 2.5 / 3.3 volt logic, 5 volt compatible | | Output Current | +/- 4.0 mA | | Input Leakage Current | +/- 10 uA | | Power on State | Default is disconnect at power on (unprogrammed FPGA) or defined by FPGA program | | Number of Channels (external interface) | 160 I/O signals, single ended, direction is configurable on a per channel basis Up to 64 I/O can be diffferential (32 differential channels) (4) I/O are single-ended or (2) differential clock inputs | | Protection | Overvoltage: -0.5V to 7.0V (input) Short circuit: up to 8 outputs may be shorted at a time | | I/O Connector | (4) SCSI III, VHDCI type, 68 pin female | | Expansion Board Interface | | Board ID | 4 bits | | Digital I/O Interface | 160 I/O, up to 84 I/O can be configured as 42 differential I/O channels | | Master Clear | From PXIe interface | | Power | +/- 12 volts, +5 volts, +3.3 volts, +2.5 volts, +1.2 volts | | Timing Sources | | PXIe Bus | 10 MHz, 100 MHz | | Internal | 80 MHz oscillator, +/- 20 ppm | | FPGA & Memory | | FPGA Type | Altera Stratix III, EP3SL50F780 | | Number of PLLs | Four | | Logic Elements | 47.5K | | Internal Memory | 1.836 Mb | | On-Board Memory | 256K x 32 SSRAM | | On-Board Flash | 16 MB | | Power | | 3.3 VDC | 3.6A typical, 4.9A max | | 5 VDC | 0.035A typical, 0.04A max | | 12 VDC (For Expansion Board) | Expansion board dependent | | Environmental | | Operating Temperature | 0° C to 50° C | | Storage Temperature | -20° C to 70° C | | Size | 3U PXI | | Weight | 200 g |
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Note: Specifications are subject to change without notice.
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